UCI-compatible chess engine with bitboard representation, negamax search, alpha-beta pruning, and piece-square evaluation.

Multi-symbol exchange with price-time priority matching, benchmarked with Google Benchmark.

Custom 32-bit RISC-V processor core from scratch.

FPGA hardware accelerator for a neural net trained in Python on MNIST digit recognition.

Wearable with flex sensors + IMU for real-time Australian Sign Language translation.

Single-cell Li-ion BMS with voltage monitoring, fault detection, and UART diagnostics.

Low-level GPIO driver with interrupt control.